Manage initnode and finalizenode in the foreachloop progress bar.

[modules/yacs.git] / src / engine / WhileLoop.cxx

diff --git a/src/engine/WhileLoop.cxx b/src/engine/WhileLoop.cxx
index 90ce94ddf7bcf2c92db6fe9f3bd605d98b7da148..e564d6051a392ca9535161e3035413a6fe6a7dbd 100644 (file)
--- a/src/engine/WhileLoop.cxx
+++ b/src/engine/WhileLoop.cxx
@@ -1,3 +1,22 @@
+// Copyright (C) 2006-2015  CEA/DEN, EDF R&D
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2.1 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+//
+// See http://www.salome-platform.org/ or email : webmaster.salome@opencascade.com
+//
+
 #include "WhileLoop.hxx"
 #include "Runtime.hxx"
 #include "OutputPort.hxx"
@@ -19,6 +38,15 @@ WhileLoop::WhileLoop(const std::string& name):Loop(name),_conditionPort(NAME_OF_
 WhileLoop::WhileLoop(const WhileLoop& other, ComposedNode *father, bool editionOnly):Loop(other,father,editionOnly),
                                                                                      _conditionPort(other._conditionPort,this)
 {
+  //Copy Data linking
+  std::vector< std::pair<OutPort *, InPort *> > linksToReproduce=other.getSetOfInternalLinks();
+  std::vector< std::pair<OutPort *, InPort *> >::iterator iter=linksToReproduce.begin();
+  for(;iter!=linksToReproduce.end();++iter)
+    {
+      OutPort* pout = iter->first;
+      InPort* pin = iter->second;
+      edAddLink(getOutPort(other.getPortName(pout)),getInPort(other.getPortName(pin)));
+    }
 }
 
 void WhileLoop::init(bool start)
@@ -33,7 +61,7 @@ void WhileLoop::exUpdateState()
     return;
   if(_inGate.exIsReady())
     {
-      setState(YACS::TOACTIVATE);
+      setState(YACS::ACTIVATED);
       _node->exUpdateState();
       if(_conditionPort.isLinkedOutOfScope())
         if(_conditionPort.isEmpty())
@@ -61,7 +89,7 @@ Node *WhileLoop::simpleClone(ComposedNode *father, bool editionOnly) const
   return new WhileLoop(*this,father,editionOnly);
 }
 
-InputPort *WhileLoop::getInputPort(const std::string& name) const throw(Exception)
+InputPort *WhileLoop::getInputPort(const std::string& name) const throw(YACS::Exception)
 {
   if(name==NAME_OF_INPUT_CONDITION)
     return (InputPort*)&_conditionPort;
@@ -94,7 +122,7 @@ YACS::Event WhileLoop::updateStateOnFinishedEventFrom(Node *node)
 void WhileLoop::checkLinkPossibility(OutPort *start, 
                                      const std::list<ComposedNode *>& pointsOfViewStart,
                                      InPort *end, 
-                                     const std::list<ComposedNode *>& pointsOfViewEnd) throw(Exception)
+                                     const std::list<ComposedNode *>& pointsOfViewEnd) throw(YACS::Exception)
 {
   DEBTRACE("WhileLoop::checkLinkPossibility");
 }