-// Copyright (C) 2006-2008 CEA/DEN, EDF R&D
+// Copyright (C) 2006-2012 CEA/DEN, EDF R&D
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public
-// License as published by the Free Software Foundation; either
-// version 2.1 of the License.
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2.1 of the License.
//
-// This library is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
//
-// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
-// See http://www.salome-platform.org/ or email : webmaster.salome@opencascade.com
+// See http://www.salome-platform.org/ or email : webmaster.salome@opencascade.com
//
+
#include "WhileLoop.hxx"
#include "Runtime.hxx"
#include "OutputPort.hxx"
WhileLoop::WhileLoop(const WhileLoop& other, ComposedNode *father, bool editionOnly):Loop(other,father,editionOnly),
_conditionPort(other._conditionPort,this)
{
+ //Copy Data linking
+ std::vector< std::pair<OutPort *, InPort *> > linksToReproduce=other.getSetOfInternalLinks();
+ std::vector< std::pair<OutPort *, InPort *> >::iterator iter=linksToReproduce.begin();
+ for(;iter!=linksToReproduce.end();++iter)
+ {
+ OutPort* pout = iter->first;
+ InPort* pin = iter->second;
+ edAddLink(getOutPort(other.getPortName(pout)),getInPort(other.getPortName(pin)));
+ }
}
void WhileLoop::init(bool start)
return;
if(_inGate.exIsReady())
{
- setState(YACS::TOACTIVATE);
+ setState(YACS::ACTIVATED);
_node->exUpdateState();
if(_conditionPort.isLinkedOutOfScope())
if(_conditionPort.isEmpty())
return new WhileLoop(*this,father,editionOnly);
}
-InputPort *WhileLoop::getInputPort(const std::string& name) const throw(Exception)
+InputPort *WhileLoop::getInputPort(const std::string& name) const throw(YACS::Exception)
{
if(name==NAME_OF_INPUT_CONDITION)
return (InputPort*)&_conditionPort;
void WhileLoop::checkLinkPossibility(OutPort *start,
const std::list<ComposedNode *>& pointsOfViewStart,
InPort *end,
- const std::list<ComposedNode *>& pointsOfViewEnd) throw(Exception)
+ const std::list<ComposedNode *>& pointsOfViewEnd) throw(YACS::Exception)
{
DEBTRACE("WhileLoop::checkLinkPossibility");
}