src/engine/OutPort.cxx

   1 #include "OutPort.hxx"
   2 #include "InPort.hxx"
   3 #include "ComposedNode.hxx"
   4 #include <algorithm>
   5 #include <iostream>
   6
   7 using namespace YACS::ENGINE;
   8 using namespace std;
   9
  10 OutPort::OutPort(const OutPort& other, Node *newHelder):DataPort(other,newHelder),Port(other,newHelder)
  11 {
  12 }
  13
  14 OutPort::OutPort(const std::string& name, Node *node, TypeCode* type):DataPort(name,node,type),Port(node)
  15 {
  16 }
  17
  18 OutPort::~OutPort()
  19 {
  20 }
  21
  22 void OutPort::getAllRepresented(std::set<OutPort *>& represented) const
  23 {
  24   represented.insert((OutPort *)this);
  25 }
  26
  27 int OutPort::edGetNumberOfOutLinks() const
  28 {
  29   return edSetInPort().size();
  30 }
  31
  32 std::vector<DataPort *> OutPort::calculateHistoryOfLinkWith(InPort *end)
  33 {
  34   if(!isAlreadyLinkedWith(end))
  35     throw Exception("ComposedNode::edRemoveLink : unexisting link");
  36   vector<DataPort *> ret;
  37   ComposedNode* lwstCmnAnctr=ComposedNode::getLowestCommonAncestor(getNode(),end->getNode());
  38   set<ComposedNode *> allAscendanceOfNodeStart=getNode()->getAllAscendanceOf(lwstCmnAnctr);
  39   set<ComposedNode *> allAscendanceOfNodeEnd=end->getNode()->getAllAscendanceOf(lwstCmnAnctr);
  40
  41   // --- Part of test if the link from 'start' to 'end' really exist particulary all eventually intermediate ports created
  42
  43   ComposedNode *iterS=getNode()->getFather();
  44   pair<OutPort *,OutPort *> currentPortO(this,this);
  45   ret.push_back(currentPortO.first);
  46   while(iterS!=lwstCmnAnctr)
  47     {
  48       iterS->getDelegateOf(currentPortO, end, allAscendanceOfNodeEnd);
  49       if(currentPortO.first!=ret.back())
  50         ret.push_back(currentPortO.first);
  51       iterS=iterS->_father;
  52     }
  53   iterS=end->getNode()->getFather();
  54   InPort *currentPortI=end;
  55   int i=0;
  56   while(iterS!=lwstCmnAnctr)
  57     {
  58       vector<DataPort *>::iterator iter2;
  59       iterS->getDelegateOf(currentPortI, this, allAscendanceOfNodeStart);
  60       if(currentPortI!=ret.back())
  61         {
  62           i++;
  63           ret.push_back(currentPortI);
  64         }
  65       iterS=iterS->_father;
  66     }
  67   vector<DataPort *>::iterator iter=ret.end(); iter-=i;
  68   reverse(iter,ret.end());
  69   return ret;
  70 }