src/engine/OutPort.cxx

   1 #include "OutPort.hxx"
   2 #include "InPort.hxx"
   3 #include "ComposedNode.hxx"
   4 #include <algorithm>
   5 #include <iostream>
   6
   7 using namespace YACS::ENGINE;
   8 using namespace std;
   9
  10 OutPort::OutPort(const OutPort& other, Node *newHelder):DataPort(other,newHelder),Port(other,newHelder)
  11 {
  12 }
  13
  14 OutPort::OutPort(const std::string& name, Node *node, TypeCode* type):DataPort(name,node,type),Port(node)
  15 {
  16 }
  17
  18 OutPort::~OutPort()
  19 {
  20 }
  21
  22 void OutPort::checkConsistency(LinkInfo& info) const
  23 {
  24 }
  25
  26 void OutPort::getAllRepresented(std::set<OutPort *>& represented) const
  27 {
  28   represented.insert((OutPort *)this);
  29 }
  30
  31 int OutPort::edGetNumberOfOutLinks() const
  32 {
  33   return edSetInPort().size();
  34 }
  35
  36 std::vector<DataPort *> OutPort::calculateHistoryOfLinkWith(InPort *end)
  37 {
  38   if(!isAlreadyLinkedWith(end))
  39     throw Exception("ComposedNode::edRemoveLink : unexisting link");
  40   vector<DataPort *> ret;
  41   ComposedNode* lwstCmnAnctr=ComposedNode::getLowestCommonAncestor(getNode(),end->getNode());
  42   list<ComposedNode *> allAscendanceOfNodeStart=getNode()->getAllAscendanceOf(lwstCmnAnctr);
  43   list<ComposedNode *> allAscendanceOfNodeEnd=end->getNode()->getAllAscendanceOf(lwstCmnAnctr);
  44
  45   // --- Part of test if the link from 'start' to 'end' really exist particulary all eventually intermediate ports created
  46
  47   ComposedNode *iterS=getNode()->getFather();
  48   pair<OutPort *,OutPort *> currentPortO(this,this);
  49   ret.push_back(currentPortO.first);
  50   while(iterS!=lwstCmnAnctr)
  51     {
  52       iterS->getDelegateOf(currentPortO, end, allAscendanceOfNodeEnd);
  53       if(currentPortO.first!=ret.back())
  54         ret.push_back(currentPortO.first);
  55       iterS=iterS->_father;
  56     }
  57   iterS=end->getNode()->getFather();
  58   InPort *currentPortI=end;
  59   int i=0;
  60   while(iterS!=lwstCmnAnctr)
  61     {
  62       vector<DataPort *>::iterator iter2;
  63       iterS->getDelegateOf(currentPortI, this, allAscendanceOfNodeStart);
  64       if(currentPortI!=ret.back())
  65         {
  66           i++;
  67           ret.push_back(currentPortI);
  68         }
  69       iterS=iterS->_father;
  70     }
  71   vector<DataPort *>::iterator iter=ret.end(); iter-=i;
  72   reverse(iter,ret.end());
  73   return ret;
  74 }