*** empty log message ***

[modules/superv.git] / examples / SyrStruct.py

diff --git a/examples/SyrStruct.py b/examples/SyrStruct.py
index bbedd4f6e1d0f2bb1dc1e998fd95e4b67d8e5eab..18091029a2dcdb66d8cbf3fc2bc4c4106e595e67 100644 (file)
--- a/examples/SyrStruct.py
+++ b/examples/SyrStruct.py
@@ -366,6 +366,7 @@ EndOfwhileNotOneK = SyrStruct.Link( EndOfifNotEvenK , EndOfwhileNotOne.Port( 'K'
 SyrComponentaContainer = SyrComponent.Input( 'aContainer' , 'FactoryServer')
 SyrComponentaComponent = SyrComponent.Input( 'aComponent' , 'SyrComponent')
 forNN = forN.Input( 'N' , 0)
+
 forNK = forN.Input( 'K' , 0)
 forNmin = forN.Input( 'min' , 5)
 forNmax = forN.Input( 'max' , 9)
@@ -386,7 +387,17 @@ SyrStruct.Run()
 
 SyrStruct.DoneW()
 
-SyrStruct.State()
+print SyrStruct.State()
 
 SyrStruct.PrintPorts()
 
+SyrStruct.Export( '/tmp/SyrStruct.xml' )
+
+SyrStruct = Graph( '/tmp/SyrStruct.xml' )
+
+SyrStruct.Run()
+
+SyrStruct.DoneW()
+
+print SyrStruct.State()
+